Exemplary embodiments of the present invention relate to a semiconductor integrated circuit having a multi-chip structure, and more particularly, to a semiconductor integrated circuit in which an internal circuit of each semiconductor chip is coupled in series to a through silicon via (TSV).
In the semiconductor industry, packaging technology for integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability. For example, the demand for miniaturization has accelerated the technology development for a package having a size close to a chip size, and the demand for mounting reliability has underlined the importance for packaging technology capable of improving the efficiency of a mounting operation and the mechanical and electrical reliability after mounting.
Furthermore, as the high performance of electrical and electronic products has been demanded with the miniaturization of electrical and electronic products, a variety of technologies for providing a high-capacity semiconductor module have been researched and developed.
To provide a high-capacity semiconductor module, the high integration of memory chips is useful. The high integration may be realized by integrating a larger number of cells in a limited space of a semiconductor chip.
However, the high integration of memory chips requires a high-level technique and a large amount of development time. For example, a minute line width is useful. Therefore, stack technology has been proposed as another method for providing a high-capacity semiconductor module.
The stack technology may include building two stacked chips into one package and stacking two single packages. However, the stacking of two single packages has a limit to reducing the height of a semiconductor package with a miniaturization trend of electrical and electronic products.
Therefore, much research is being actively conducted on a stack package and a multi-chip package, in which two or more semiconductor chips are mounted in one package.
The multi-chip package may be typically fabricated by the following methods. First, several semiconductor chips may be simply arranged on a substrate and then packaged. Second, two or more semiconductor chips may be stacked in a multilayered structure and then packaged.
As an example of the second method, a structure using a through silicon via (TSV) has been proposed. A package using the TSV is realized by the following process. First, a hole is formed in a semiconductor chip to pass through the semiconductor chip, and the hole is then filled with a conductive material to form a TSV. The upper and lower semiconductor chips are then coupled through the TSV.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor integrated circuit having a multi-chip structure using TSVs.
Referring to FIG. 1, a multi-chip package 10 using TSVs includes a plurality of semiconductor chips 12 and 14 stacked on a substrate. Each of the semiconductor chips 12 and 14 includes a plurality of through electrodes 16 formed by filling the TSVs therein. Therefore, the semiconductor chips 12 and 14 are stacked in such a manner that the through electrodes 16 disposed at the corresponding positions are coupled to each other.
A plurality of bump pads 18 are formed over the semiconductor 12 so as to maintain a predetermined distance between the respective semiconductor chips 12 and 14. Therefore, the first semiconductor chip 12 having the TSVs 16 formed therein is coupled to the second semiconductor chip 14 through the bump pads 18. That is, the first and second semiconductor chips 12 and 14 are coupled through flip-chip bonding.
In the multi-chip package using the TSVs, the electrical coupling is achieved through the TSVs. Therefore, electrical degradation may be substantially prevented to increase the operation speed of the semiconductor chips, and the miniaturization may be achieved.
In the conventional semiconductor integrated circuit having a multi-chip structure, however, the TSVs are formed through the uppermost chip to the lowermost chip and then filled to form the through electrodes, and internal circuits of the respective chips receive a voltage signal in parallel through the through electrodes. In this case, in order to control the voltage signal of the through electrode and apply the controlled voltage signal to another chip, another through electrode is required for only the controlled voltage signal.
Such an increase of the number of through electrodes may reduce the performance of the circuit in terms of area and fail rate. Furthermore, when different electrical signals are to be applied to the respective chips through the through electrodes, the chips need to have different structures. In this case, a separate patterning process may be useful. Accordingly, a mask for the pattering process may be separately formed. This results in a high processing cost.
Furthermore, while the patterning process is performed, the position of the mask may be changed depending on the stack positions of the semiconductor chips. Therefore, the mass production efficiency decreases, and the cost inevitably increases.